Author: Francesco Di Tolla
Date: 05:53:35 07/09/99
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>Look at http://www.rebel.nl/bench.htm and you will see that the 450mhz K6-2 >edges out (barely) a 450mhz Xeon despite 512K cache running at full processor >speed and the K6-2 not having the 256K cache of the K6-3. This is on Rebel10. > >Apparently, in this case, it is the L1 cache where half is reserved for >instructions, not data that makes the biggest difference. The other cache seems >to vacate instructions frequently by the transposition table accesses. > >As for cstal, apparently the programmer is doing something right if he can >achieve that big of an improvement over the K6-2 with the K6-3. It has been my >experience that programmers generally do a poor job of taking advantage of the >speedups possible with cache. Cstal seems to prove this. This is bullshit (this programs do not fit in the primary execution cache in any case). You can't compare two car-engines just looking at the crossection of the fuel injection pipes. The entire design of the engine makes the main difference. Of course if your pipe is two small you won't have optimal results, but that is a second order... The two cpus have two diffent cores. Among the many factors, the first issue that changes the speed of interpretation of a code is the design of the core itself (how instructions are interpreted and scheduled). K-7 will have a totally new core (which could be the evolution of the K5, since usually two temas work in parallel to develop new CPU faster). And who knows, may be Ed's code will like it, may be not. ciao Franz
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