Author: Tim Mann
Date: 18:33:02 09/15/99
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>I wouldn't be surprised if some such sequence was fastest on the Pentium III >and Athlon as well, even though they don't have 64-bit arithmetic units so more >instructions would be needed... Oops, the above paragraph is bogus; sorry. For any x86 chip that has the instruction implemented in hardware, then of course using that instruction will almost certainly be fastest. (More on this below.) Of course, in this case you had to write a little code to do a 64-bit FirstOne using the 32-bit ffs instruction, and maybe that code could be tweaked a bit more, but an expert on x86 implementations would have to comment on that. Another thing to watch out for is how the instruction is emulated. There are basically three possibilies: (1) It's implemented with hardwired logic in the arithemetic unit and is about as fast as other arithemetic operations, say somewhere between the cost of an integer add and a floating point add. (2) It's implemented in microcode inside the chip, essentially triggering a loop that runs entirely inside the chip. I don't know if chip designers really do this anymore. (3) It's implemented by having the operating system catch an "unimplemented instruction" trap and emulate the instruction in software. Here (1) will surely be much faster than any software implementation, (2) will almost surely be faster unless the engineers did a bad job writing the microcode, and (3) will be slower than an inline software implementation because of the overhead of handling a trap. When the documentation says something is a "slow instruction," I really can't guess which of these cases is meant, so you'll have to experiment to find out what is best on the various chips you have access to. --Tim
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