Author: Bo Persson
Date: 11:18:15 09/21/99
Go up one level in this thread
On September 20, 1999 at 10:02:50, stefan wrote: >best and worse case? >Thank you >stefan plenkner Hi Stefan! The exact timing is hard to tell, especially on the newer chips with cache timing and out-of-order execution. On the PPlain and P5MMX Intel says 11+2*n clocks, where n=# of zeros skipped. This is really, really slow! On the P6 architecture (PPro, PII, PIII, Celeron) the instructions take 1-2 clocks, which is really, really fast! :-) I haven't seen any K6 timings from AMD, only that BSR/BSF are "vector decoded", which means that they are translated into several micro ops. Not too good. My bitboard tests shows that on a Pentium 133 MHz, using BSR/BSF is *much* slower than a table lookup. On my K6-233 it's about even money. On a PII-400, using BSR/BSF is *very* fast. Bo Persson bop@malmo.mail.telia.com
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.