Author: Dezhi Zhao
Date: 23:04:54 10/15/99
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On October 15, 1999 at 11:17:08, Robert Hyatt wrote: >On October 15, 1999 at 11:07:20, Dezhi Zhao wrote: > >>On October 15, 1999 at 09:12:42, Robert Hyatt wrote: >> >>>On October 15, 1999 at 06:20:55, Jeroen van Dorp wrote: >>> >>>>Is that so? >>>>Is a Pentium II @400 3 times faster than a Pentium 133? >>>>I think it is at least 6 times as fast >>>>Older systems will have slower ram (e.g. EDO) and lesser RAM installed. >>>>Also if your using a 33MHz motherboard for your P133 and a 100MHz bus speed for >>>>your PII@400HMHz (with DIMM)it will exceed that speed . >>>> >>>>Jeroen ;-} >>> >>> >>>I would put the difference it 5X, based on lots of testing here, so long as >>>he means PII at 400 (or PIII). The original pentium pro was (for crafty) >>>exactly 2.5x faster than a P5/133. The PII/400 is 2x that. >> >>I think the diffierence is around 3.4X. PC100 ram and bigger on-chip cache >>only contribue 14% in my tests with my own program. > > >there is _much_ more difference internally that just faster clocks. The PPro/ >PII/PIII has a much better cpu 'core' that executes instructions out of order, >and up to three at a time. The older P5/133 had a simple dual-pipe architecture >that was much less efficient. > > > >> >>For Crafty I think the bsf/bsr contribute to the difference another >>10%. I believe speed is mainly clockwise for chess program. And level 1 >>cache is the second important factor. PC 100 ram speeds up very little. > >I didn't use bsr/bsf when I was on the P5/133, nor did I use it on the P6/200 >when I did the 2.5x benchmarking. Bruce also got roughly 2.5x faster than a >P5/133 when he moved Ferret to the P6/200 IIRC. > >however, back to the P6/PII vs P5. There is much more than just raw clock >speed at work, as I said. The P6/PII/PIII simply has a much better internal >CPU architecture that is overall much faster. If you only get 3+x going to a >PII/400, you are probably not utilizing cache very well, so that you are >totally memory-bandwidth bound. Some careful analysis and tweaking can get rid >of a lot of that. Just remember that the pentiums all fetch 32 bytes at a >time. Put things close together if you need them in the same piece of code, >so that one cache line fill will grab 32 useful bytes, and not just 4. > Yes. I do understand the CPU architecture difference. I coded much of the speed-critical parts in asm, 2 versions, each optimized for P5 and P6 seperately. So I believe there is no big problem of code cache for my program. All the critical sections will fit the small code cache. For P6, out of order executions, register renaming don't help very much, becuase of many dependent chains. Maximum three instruction throughput per cycle does not happen very often either. But you still remind me of the data cache. I will check with my data fetch again, to see if there are big potentials in data cache. However, it is more difficult to utilize the data cache efficiently. Hash probes often crash the data cache and many data is waiting for it. > > > >> >>So for crafty, I guess the difference would be about 3.9X. >>Are there any data to support my calculations? > >No. I have a P5/133 here at uab. I ran a quick test position and got >just over 32,000 nodes per second. I ran the same test on my P6/200 box >here and got 82,000 nodes per second. On my quad xeon, using one cpu, this >same test got 165,000 nodes per second. which is roughly 5x overall, and >2.5x for the P6 vs the P5 > > Probably, crafty has some critical code sections bigger than code cache of Pentium plain which is only 4K. Some critical functions may not fit this 4K well. When you go to PII, the code cache becomes 16K (8K for PPro) which will improve the performence greatly. Code fetch and decoding is often the bottle neck for Pentium family processors as said in the optimization manuals. Thanks for your test data. I will investigate it again and post my results again. Dezhi Zhao > > > > >> >> >>Dezhi Zhao
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