Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: Chess benchmarks on PIII coppermine ?

Author: Vincent Diepeveen

Date: 03:21:44 12/07/99

Go up one level in this thread


On December 06, 1999 at 16:18:39, Dann Corbit wrote:

>On December 06, 1999 at 08:39:37, Vincent Diepeveen wrote:
>[snip]
>>More registers kick butt bigtime (unlikely that
>>intel changes this till the merced comes out as this would require new
>>compiler and incompatibility with current software), but i have no
>>idea how much it would speedup my program.
>Except when you change context from thread to thread.  That why the 256 register
>SPARC is handicapped for multiple CPU's.  A context switch is very expensive.
>Imagine a million registers and going from thread to thread for an easy mind
>experiment about why lots of registers is not always a good thing.
>[snip]

pushing a few registers won't be a problem. i didn't test at multiprocessor
sparcs, i would have like that though...
...alpha seems also a lot slower at more than 1 cpu btw.

single cpu 667Mhz 21264 experimental at icc: 850k nps
dual  cpu 667Mhz 21264 experimental: 1M to 1.2M nodes a second

(crafty of course)



This page took 0 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.