Author: Eugene Nalimov
Date: 09:17:56 12/07/99
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IA-64 has 128 integer registers that are visible to the application. Of those part will be used to generate addresses in memory (as the only addressing mode is register indirect with possible postincrement/postdecrement), but even taking that into account you'll have A LOT OF registers. Eugene On December 07, 1999 at 04:12:20, Tom Kerrigan wrote: >Intel says a lot about how many registers the "Itanium" has, but they only make >a small fraction of them available to the user. The design is supposed to be >really great because when it gets to a branch, it can start working on both >paths while the branch condition is still being evaluated. You can imagine this >sucks a lot of registers... > >(I'm just repeating some secondhand information. I could be totally wrong...) > >-Tom > >On December 06, 1999 at 08:39:37, Vincent Diepeveen wrote: > >>On December 05, 1999 at 20:31:41, Jeremiah Penery wrote: >> >>>On December 05, 1999 at 19:41:00, Vincent Diepeveen wrote: >>> >>>>On December 05, 1999 at 12:59:09, Werner Schuele wrote: >>>> >>>>>Can anybody post chess-benchmarks for PIII 600E or PIII 650/700?. >>>>>I wonder if Athlon or PIII is the better chess-processor. >>>>>Thanks >>>>>Werner >>>> >>>>Athlon is a gift from heaven. >>>> >>>>It's 15.5% faster than a PIII for DIEP, >>>>and i can only pray that a dual and quad motherboard for it >>>>gets out real soon and competes with intel in such a way that >>>>quad motherboards get cheaper, yes even octo motherboards... >>>> >>>>Note that celeron is also quicker than PIII, about 7.2% for DIEP, >>>>but parallel of course it doesn't get near that, it's about >>>>as fast as a PIII for the parallel version of DIEP, so when >>>>talking about parallellism, please let the dual boards already come >>>>from AMD... ...especially now that a 1 Ghz AMD is available (kryoteched >>>>cooled and overclocked SuperG stable at 1 Ghz, see www.kryotech.com) >>> >>>Have you tried Diep on the Coppermine PIIIs, as opposed to the Katmai ones? I >>>saw benchmarks (from PC Magazine or something...) where the Coppermine was up to >>>40% faster in raw integer/FP calculating speed than a Katmai PIII at the same >>>speed (MHz). This is due to a number of factors, which I won't go into now... >>>With the Coppermine, the PIII is just as fast as the Athlon. >> >>Wherever i look, i can't find a single dealer which has a coppermine >>available. This is like saying: wait for the k8 to come out. Let's >>get real and clearly distinguish between processors that we can buy >>and processors that get out one day. >> >>Note that intel promised till few months before it was available >>that Katmai would be 15-25% faster than a PII, yet for integer instructions >>it appeared to be 100% the same as the PII. Let's relax and wait for the >>coppermine to get introduced and then draw some conclusions. >> >>For now my favourite 2 processors are the K7 and the 21264. >> >>Note that from AMD i wasn't given any details how their branch prediction >>works, in contradiction to dec-alpha for the alpha 21264 which seems to >>have a superb form of branch prediction. Took AMD 1 month to reply to >>an email of mine. It's a 2k big table that's all i know. >> >>The penalty for a misprediction is *at least* 10 clocks at AMD, >>so a clock more than what PIII does give. So being 15.5% faster than >>a PIII for DIEP is theoretical kind of weird. >> >>Except for the 21264 which does 4 instructions a clock, they all do 3 >>instructions a clock. >> >>The interesting details list to know from any CPU for chessprograms: >> - #instructions a clock >> - number of integer registers (merced gonna have 128!!!!!) >> - L1 code/data cache sizes >> - L2 speed and size >> - new form of branch prediction (hopefully copied from dec alpha?)? >> - #entries for Branch prediction table (512 only for the PRO/PII/PIII). >> - smallest delay for a branch misprediction >> - 64 bits? >> >>Expected speedups for possible changes assuming the processor is a PIII >>and then gets next projected on DIEP on a new CPU with just one change: >> >>If a CPU does 4 instructions a clock instead of 3, then that obviously >>should speed up roughly 30%. >> >>More registers kick butt bigtime (unlikely that >>intel changes this till the merced comes out as this would require new >>compiler and incompatibility with current software), but i have no >>idea how much it would speedup my program. >> >>making L1 cache from 32 kb to 128 kb gives nearly 10% speedwin. >>Speeding up the L2 cache to processor speed (doubling in speed), about 7% >>speedwin (if both L1 cache gets bigger and L2 gets faster then i guess total >>speedup is less way less than 17%). >> >>new form of branch prediction (let's take the alpha branch prediction) >>i can only guess here bigtime: 25% speedup? >> >>increasing BTB (branch target buffer on intel processors) or branch >>prediction table from 512 to 2048 ==> 10% speedup. >> >>If hardly delay for branch mispredictions i'd >>expect my program to get 2 times faster... >> >>Getting a 64 bits processor is interesting to know for Bob, >>not for DIEP though. >> >>What i don't have are these details for the SUNSPARC processor. >>For crafty this processor sucks bigtime, even though it's a 64 bits >>processor. >>DIEP isn't fast either on these processors, though it's not that slow. >>a 300Mhz sun performs like a 233Mhz PII for DIEP nowadays or a bit >>faster than a pro200Mhz. At the sun i used gcc 2.95.1, and considering >>this compiler is at intel processors around 8% slower than the visual >>compiler, that would make the sun look like a bit better: >>==> 233 x 1.08 = 252Mhz PII which means that a PII at the same Mhz is >>less than 20% faster. >> >>Vincent
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