Author: Robert Hyatt
Date: 14:33:36 12/16/99
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On December 16, 1999 at 15:19:01, Greg Lindahl wrote: >On December 16, 1999 at 14:50:53, Robert Hyatt wrote: > >>The real headache with FPGAs is that they have some important missing things >>that the DB chips have. > >Don't get caught up in the straw-man argument here -- there's no reason that >someone using FPGAs would not put functions on the FPGA more suitable for FPGAs. >Things have changed since DB: processors are faster, the busses have higher >bandwidth and lower latency (DB was MCA, yes?), the interconnect I use is only >as fast as DB's IBM SP (albeit with lower latency). These factors all mean that >a different design is likely. > >I only asserted that the overall plan was possible, not that I could definitely >put an exact replica of DB's chip onto an FPGA. And so there's not much point >proving or disproving the assertion that I'm naieve for proposing something I >never proposed. If you wanted to discuss the real issue, then discuss what you >might put onto an FPGA that would produce speedup without loading the host >processor too badly. > >-- greg Sure... But memory is _essential_. You have to maintain a chess position. You have to maintain a list of previous positions so you can detect draws by repetition. You have to maintain a 50-move counter. And you have to maintain a set of evaluation weights that can be adjusted... All of that spells memory. Belle was made from zillions of FPGA's back in the very late 70's and it did work. But the lack of memory caused some significant extra circuitry... And the goal here _has_ to be to come up with a single chip, else DB is going to totally blow the design away... as going off-chip is just about as bad as going off-board, or off-machine...
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