Author: Martin Grabriel
Date: 05:45:49 12/17/99
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Thanks Jeroen You are an angel. I shouldn't have make fun of you and call you the ICQ pic guy at rgcc...:) On December 17, 1999 at 05:40:12, Jeroen van Dorp wrote: >On December 16, 1999 at 23:15:12, Martin Grabriel wrote: > >>Hi >>Can you teach me how to change the CAS Latency or speed? > >It's in the BIOS setup menu. > >Mostly the procedure is to start your computer and hit <del> of sometime F1 or >F2. The computer tells you that at the start up screen "hit <---> to enter >setup" or so. > >Select the "Chipset Feature Setup" and there you'll find it. >But most BIOS versions will give you a message at startup when your CAS Latency >time is wrong. > >Remember that roaming around in your BIOS can result in unexpected software >glitches. Remember what you changed, and *that* you changed. > >To have any idea what you are changing, read the following: > >"CAS Latency is one of several performance related timings for SDRAM. This >measurement is the time it takes to strobe in the Row Address, and to activate >the bank. When a burst read cycle is initiated, the addresses are set up and >RAS\ and CS\ (chip select) are held low on the next clock cycle (rising edge of >CLK), thereby activating the sense amplifiers on the bank. A period of time >equal to tRCD (RAS\ to CAS\ delay) must pass after which CAS\ and CS\ are held >low (again, at the next clock cycle). After the time period for tCAC (column >access time) has passed the first bit of data is on the output line and can be >retrieved (at the next clock cycle). The basic rule is that CAS latency times >the clock speed (tCLK) must be equal or greater than tCAC (or CL x tCLK >= >tCAC). This means that the column access time is the limiting factor for CAS >Latency." > >Jeroen ;-} >------------------------------- >The ChessBrat at: >jimvandorp@wxs.nl >http://zip.to/jeroen >ICQ#45740870 >-------------------------------
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