Author: Robert Hyatt
Date: 18:34:15 12/20/99
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On December 20, 1999 at 19:38:30, Greg Lindahl wrote: >On December 20, 1999 at 19:23:27, Robert Hyatt wrote: > >>probably more than you think. IE you have to pass the repetition list, which >>can be (in the case of Crafty) 800 bytes. plus 4 bytes per ply as the hardware >>will need access to the moves to back up the PV. plus other things as well. >>Turns out to require quite a bit of 'stuff'. > >As usual, you're making an assumption about how much of the algorithm goes onto >the chip. What if you don't have to pass the repetition list? Then how much data >is passed? Depends. But if you don't pass the repetition list, then you aren't planning on doing an 'engine in hardware'. Hsu tried that in the first version of his hardware and regretted it until he fixed it in deep blue hardware. As I said before, if you don't put the _entire_ engine on the board, then the speedup is not going to be particularly attractive. IE a multiprocessor PC isn't going to respond well to a set of these boards sitting on a shared PCI bus. And will likely run slower with than without, since the PCI bus isn't exactly blazingly fast, compared to memory bandwidth, which isn't exactly blazingly fast compared to cache/cpu bandwidth... So instead of bantying words, exactly _what_ are you suggesting putting on this FPGA-based board? IE rather than my attempting to guess, how about a specific speculation. Because anything less than a "full chess engine" isn't going to offer any super-performance. At least enough to make the cost/effort worthwhile. As I said, 20 years of chess-specific hardware development has pretty well proven that it takes a complete engine to make it worthwhile... And as I also said, a complete engine is non-trivial...
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