Author: Vincent Diepeveen
Date: 06:13:18 12/21/99
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On December 20, 1999 at 21:37:43, Robert Hyatt wrote: >On December 20, 1999 at 19:40:41, Greg Lindahl wrote: > >>On December 20, 1999 at 19:25:17, Robert Hyatt wrote: >> >>>He is talking about the hash table. If you punt on that, you take a huge hit >>>in performance. The only way to make it up is to do dozens of chess processors >>>like DB used. This is assuming that the chess processor is really doing a true >>>alpha/beta search, and not just pieces of this (like evaluation). >> >>Again, you're making the assumption that you have to put the hash table on the >>chip or not use it at all. That isn't necessary; you could put just the >>evaluation function onto the chip, and do the hash lookup on the main processor. >>In order for that to be interesting, the evaluation function has to be a large % >>of total time, which is true for some existing computer algorithms (but not >>Crafty.) > >Crafty's eval is 50% of the total time. Nobody is over 90% of total time in Diep is at 90% in middlegame/opening. A lot less in endgame however, but endgame is less interesting as we all already search quite deep there compared to start of the game. >eval. So there isn't a lot of room for improvement there. The problem that >you may be overlooking is this: Suppose a very fast program (fritz) searches >300K nodes per second with almost no eval. Your hardware won't help much. >Suppose another program searches at 30K with 90% of the time spent in eval. >You speed that program up to almost 300K. That isn't enough to make a huge >difference, particularly when someone can compile on other platforms (like >the 21264) and get a big boost there as well... You have a point here when looking to the future. Same is true for deep blue however, it just searched 11 ply, as they started designing in a time where nullmove hardly was known. Diep evaluates 2000 to 4000 full evaluations a second at a PII450 (middlegame). A K7 is 15.5% faster. Let's assume 21264 is 30% faster than a PII/PIII for DIEP. That would mean still 2600 to 5200 full evals a second. With 1 usec an evaluation from the PCI bus and another usec or so for the hardware we still burn at most 3 usec (1 for a message to the processor, 1 for the FPGA eval itself, and 1 back). if 3 usec = 0.000003 seconds an eval then we can do this 333k times a second. Now this can speedup DIEP nearly 10 times. At a single processor system which everyone can afford this is an amazing speedup, as DIEP then gets nearly 3 ply deeper. It will take some time before processors are also 10 times faster and affordable. I do see the use of writing *everything* in hardware. that would allow instead of a 100k nodes a second speeds around a million nodes a second. So another 10 times faster. However a big problem is the many years such a design takes. It needs a professional FPGA programmer to do it, and he must be very good at it too. Vincent
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