Author: David Blackman
Date: 22:49:14 12/21/99
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On December 21, 1999 at 10:40:50, Robert Hyatt wrote: > >I am more concerned about a different problem. This ram is single-ported. Yet >a good hardware eval will continually be reading bits and pieces out of this >memory... how many pawns on this file.. which side has the left-most passed >pawn or candidate, which side has the right-most passed pawn or candidate... > >This means that memory is going to be accessed from many different eval >components. And I don't see how to do this efficiently, as it is going to be >a serial bottleneck. In a non-FPGA design, you could distribute this memory >around so that this isn't a bit handicap, but here it is. I've been reading about the latest FPGAs from Xylinx and other companies. Which is not quite the same as actually using the things :-) But it appears they are getting really serious about RAM on FPGAs these days. First there is a lot of it available. Certainly up to 10s of KBytes on many models. Second, for at least some models it is dual port ram, or at least 2 read or 1 write per cycle. Third, most of the models i read about partition the ram into lots of fairly small cells, each independant and connected to a local array of processing elements nearby on the chip. Each of these RAM/processing element chunks seems to work in parallel, so the total bandwidth to all the ram on the FPGA must be enormous. Tricky if you want a single large unified address space, but great if you have a lot of small parallel processes each needing memory access. Now it looks to me that programming one of these efficiently would be a bit tricky, and certainly very different to programming a conventional CPU. But i reckon if you could figure it out, you could get a FPGA to run chess really, really fast. If the figures quoted by Xilinx are just the usual marketing hype, and not total outright lies, then their top of the line FPGAs are better than the ASICs used by Deep Blue in almost every way. More gates, more memory, faster, etc. Not quite as flexible of course, but the hardware is grouped in a reasonably convenient way and there is so much extra resources available that i think you would have to come out ahead. FPGAs have come a long way in the last few years.
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