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Subject: Re: FPGAs playing chess--an expert opinion

Author: Robert Hyatt

Date: 11:03:21 12/22/99

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On December 22, 1999 at 10:20:03, Albert Silver wrote:

>On December 21, 1999 at 23:20:00, Robert Hyatt wrote:
>
>>On December 21, 1999 at 18:48:15, Greg Lindahl wrote:
>>
>>>On December 21, 1999 at 18:03:10, Robert Hyatt wrote:
>>>
>>>>  And they generally
>>>>don't propose solutions until they have a pretty clear understanding of the
>>>>_problem_.
>>>
>>>There's your problem -- you think I'm "proposing solutions" when I'm just
>>>brainstorming as a means of learning.
>>>
>>>I've pointed this difference out several times. Maybe someday you'll notice.
>>>
>>>-- g
>>
>>
>>No.. every time I point out a problem, you respond "that might not be a problem
>>with the right design approach."
>>
>>Not very convincing, IMHO...
>>
>>I at least understand the problem domain _clearly_.  And would be interested
>>in seeing you get something going, although I suspect it will be problematic
>>to get money to do it.  But that aside, the idea is interesting.  But the
>>problems are significant.  Otherwise we would be up to our armpits in these
>>things already...  when you think about it.
>
>The question begs asking so I'll ask it: If you were to try to build the next
>super duper ultra chess machine, and provided costs were not the biggest issue,
>how would you go about it? How would you pick up from Deep Blue? I realize this
>is completely hypothetical, and that any ideas you had would still need to bear
>testing, but the question remains: what would you do?
>
>                                     Albert Silver

I think that DB was the best that can be done from a hardware design point of
view.  Of course, we could use .18 micron (or smaller) fab processes and speed
up the chips significantly.  Hsu speculated at least a factor of 10-20 would be
doable.  But as far as the hardware design goes, it does just what it needs to
do.  Yes it would be nice to get singular extensions into the hardware so that
the last 4-6 plies (if the processors are 20+x faster, they would search about
2 more plies deeper than at present, so rather than the last 4 plies, they would
do the last 6 plies probably) would be the same as the first N-(4-6) plies.

I suspect that is doable at the smaller gate sizes possible in .18 (and smaller)
ICs.  Then the issue becomes the price of the 'host'.  As to go real fast, you
want to drive many of the chess processors in parallel, and that takes a very
fast host, probably a machine along the lines of the IBM SP or something.  Maybe
a shared-memory 8-way xeon box might also work as a bottom-end "deep blue junior
plus" type machine...



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