Author: Amir Ban
Date: 03:20:22 01/25/00
Go up one level in this thread
On January 25, 2000 at 04:35:33, David Blackman wrote: >On January 24, 2000 at 12:20:12, Robert Hyatt wrote: > >>On January 24, 2000 at 09:57:58, Amir Ban wrote: >>>"I'll bet that I have several evaluation terms that are not practical for them >>>to compute." >>> >>>Amir >> >> >>Let me repeat also: "There is _nothing_ you can do in software that they can't >>do in hardware in _far_ less time. _absolutely nothing_." That is the benefit >>of doing what they did in hardware. Never a question of "can I afford this or >>will it slow me down too much?" Only a question of "is this worth the time it >>will take to design it?" > >I wonder if there is some stuff that you want to eval in about 1% of positions. >You just have a quick if statement mostly, but in 1% of positions it triggers >and you do 500 lines of code. In a software program, this costs you very little >except RAM, which is cheap. > >In hardware, it costs you for chip area and partly for power, even for those 99% >of positions that don't use it. > >If i was doing hardware, i'd avoid most of these. In software, i'd put them in >if i had the time and the knowledge. > >I can't think of any good examples right now, but i'm sure the slow/smart >brigade use plenty of them. Yes, this makes a good point. I can't directly answer "what can't they do ?" without studying in depth the chip design, and probably needing more information than was ever published, but I know on general grounds that to say that the chip could do anything and in zero cost is just hype. The hardware/software tradeoff doesn't work this way. Hardware is not only more expensive, but also less flexible. In software you can do anything. In hardware you have to adopt some model in which you will try to fit the features. If your feature fits the model, great, and then the cost will be about zero. If it doesn't fit the model, forget it. Even from the brief description available for the chip I can see the model in broad outline. The main part of it is piece-square tables, which are in RAM, and most probably downloaded from the host when the chip gets a position. This is a sensible and flexible way to do this, but it means the chip doesn't do true node evaluation, but is a hybrid preprocessor (like Junior). There is a second part of the evaluation that falls under the heading of "slow". If I remember right, it takes three cycles, and relies on a pipelined row or column scan. They have an impressive array of features they say is done this way, but it's clear this relies on modeling the feature to fit the particular method of pipelined scanning. A feature that won't fit into this mold won't fit anywhere. Another really obvious point is that even a feature that fits perfectly into the model, but is not currently implemented would need a 6-month cycle to implement, more if first silicon fails. This is not so practical if you have a year between matches that you want to devote to working with grandmasters to improve your evaluation. I'm sure that they did their best to avoid this dilemma, by making the chip as parameterized and customizable as possible, but by doing that they forced upon themselves a constrained model, and only bought themselves a small percent of the flexibility and programmability that a software developer has for free. Finally, since it's Bob asking the question, I suspect he's only aware of what crafty can do, and regards everything else as not practical in software. I see this, for example, when I say up in this thread that I can do something for free, and Bob "refutes" this by telling that he's done it in crafty and it's not free. It's in line with his theory that we all started by downloading the crafty sources and built on top of that, but this is not true of course. Amir
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