Author: Dann Corbit
Date: 16:00:43 01/26/00
Go up one level in this thread
On January 26, 2000 at 18:33:41, Tom Kerrigan wrote: [snip] >Now we can make the following assumptions: >* one hertz = one instruction (good enough) >* Bob is correct -> FHH meant 40,000 DB instructions >* DB chip searched at least 2M NPS > >Here is the simple arithmetic based on these assumptions: > >(2M nodes/sec) * (40k instructions/node) = 80G > >In other words, the DB chip would have to run at 80 GIGAhertz to search 2M NPS, >which the obviously did not do. What if the circuit were massively parallel? If (for instance) 10K instructions can be run at once, then it is 80MHz. I don't know anything about the design, but it seems possible [sort of]. It certainly does not sound likely, but without the context of what Hsu actually said, I can't be sure what was meant. But then, I did not read the threads in question. I think Bob may have reviewed FHH's book, and maybe he got the idea from there. What is the thread title. I'd like to take a look.
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