Author: Ricardo Gibert
Date: 22:36:13 02/15/00
Go up one level in this thread
On February 16, 2000 at 00:26:19, Christophe Theron wrote: >On February 15, 2000 at 22:45:28, Tom Kerrigan wrote: > >>On February 15, 2000 at 20:42:43, Ricardo Gibert wrote: >> >>>MIPS VR4121 is a 64 bit CPU according to NEC. Look at >>>http://www.nec.com/Semiconductors/categories/679/981008.html >> >>You're right... Hmmm... I wonder what the "64 bit" measures. Maybe memory >>interface? Because it seems pretty silly to have a full-blown 64-bit embedded >>processor, when your desktop machine is still 32-bit... >> >>-Tom > > >Wait a minute. The VR4121 processor claims pin-to-pin compatibility with the >VR4111. And the VR4111 is a "false 64 bits" processor. Operations can be done on >64 bits internally, but the data bus size is 16 or 32 bits. That is, there is a >serious bottleneck between the processor and the memory when it comes to 64 bits >values. > >I'm not even sure that this processor really supports clean 64 bits operations. >All the docs I have mention 16 and 32 bits long instructions. How do you perform >a move immediate with a 64 bits value if your instruction length is limited to >32 bits? ??? Addresses can _referenced_ by less than 64 bits. For example, you can load a 64 bit register with a 16 bit address reference. > >And don't count on the 8Kb internal L1 data cache to store all the data needed >by Crafty... > >A bitboard program looks like a poor choice for this architecture. Why? The VR4111 has a 5 stage pipeline for instance. See the Nalimov post in this thread. > > > > Christophe
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.