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Subject: Re: Intel Willamette and chess

Author: Eugene Nalimov

Date: 22:52:58 02/18/00

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On February 19, 2000 at 01:42:19, David Blackman wrote:

>On February 18, 2000 at 21:11:58, Tom Kerrigan wrote:
>
>>
>>You just got the docs for the SIMD instructions? Where? Does it look like the
>>chips have a FindFirstBit instruction, etc.?
>>
>>-Tom
>
>I didn't see the docs, but read some of the discussion. The thing has a 20 stage
>pipeline. They claim they use every trick there is for branch prediction, but
>still, you should have a close look at your program and ask how you can make
>your branches easier to predict (or remove them completely). Also, how you can
>overlap various computations so you don't get 20 clock pipeline stalls. That
>kind of stuff is probably going to be the most important optimisation for most
>future chips, as pipelines get longer.

Optimizarions to hide memory latency are more important.

Eugene
>So, it's time to re-evaluate 12x10 vs 0x88 vs bitboards vs attack maps in the
>light of long pipelines. I suspect bitboards or attack maps look better for eval
>purposes (but they were always good there).



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