Author: Tom Kerrigan
Date: 13:29:19 03/02/00
I was just looking at this document: http://www.mips.com/products/5Kc.pdf It says the die size of this 64-bit core is 3 mm^2 (0.18 um)!! I believe the Celeron die size is ~80 mm^2. So it seems like you should be able to put a dozen of these cores onto one chip with room left over for a big wad of L2 cache. That would be pretty awesome for a chess program... -Tom
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