Author: Peter Klausler
Date: 17:19:17 06/03/98
Go up one level in this thread
On June 03, 1998 at 18:21:00, David Fotland wrote: >The problem is that if you want to issue 4 instructions in parallel they >have >to be independent. This is very hard on x86 because there are only 8 >registers. The fast 4 issue superscalar RISC all have 32 registers, and >EPIC has 128. The small register size really slows down x86, and it's >very >hard to change the number of registers without making a new instruction >set. > >David Fotland (one of the Merced/IA64/EPIC instruction set designers) And if you want to execute 30-50 instructions per cycle? VLIW architectures with unified register files run up against physical limitations on the numbers of read and write ports that can be implemented. And statically scheduled code can't adapt to unpredictable memory latencies. I think that VLIW is a fine approach for high performance within the limitations of memory bandwidths imposed by the pins of a single-chip processor with external memory. For more ambitious memory systems, or for processors implemented on die with DRAM arrays, the limitations of VLIW manifest themselves quickly, and other approaches are required. -Peter Klausler (Cray compiler guy and instruction set architect)
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.