Author: David Fotland
Date: 14:06:05 06/04/98
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On June 03, 1998 at 20:19:17, Peter Klausler wrote: >On June 03, 1998 at 18:21:00, David Fotland wrote: >>The problem is that if you want to issue 4 instructions in parallel they >>have >>to be independent. This is very hard on x86 because there are only 8 >>registers. The fast 4 issue superscalar RISC all have 32 registers, and >>EPIC has 128. The small register size really slows down x86, and it's >>very >>hard to change the number of registers without making a new instruction >>set. >> >>David Fotland (one of the Merced/IA64/EPIC instruction set designers) > >And if you want to execute 30-50 instructions per cycle? That's a whole different question :) I just wanted to point out that it isn't so easy to get modest parallelism out of x86. I guess there are some scientific codes with 30-50 ILP, but I don't think anyone knows how to find that much ILP in typical Microsoft or Oracle code :) > >VLIW architectures with unified register files run up >against physical limitations on the numbers of read and >write ports that can be implemented. And statically >scheduled code can't adapt to unpredictable memory >latencies. Both valid points that generated a lot of discussion as the instruction set was being defined. I don't think anything is public yet about how EPIC addresses them, so I can't comment. > >I think that VLIW is a fine approach for high performance >within the limitations of memory bandwidths imposed by the >pins of a single-chip processor with external memory. For >more ambitious memory systems, or for processors implemented >on die with DRAM arrays, the limitations of VLIW manifest >themselves quickly, and other approaches are required. Agreed, but the single chip microprocessor with external memory is the market HP and Intel are interested in. There is always room for quite different architectures to address the grand challenge scientific problems. David > >-Peter Klausler (Cray compiler guy and instruction set architect)
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