Author: Keith Evans
Date: 12:39:47 10/11/02
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On October 11, 2002 at 12:12:18, Robert Hyatt wrote: >On October 11, 2002 at 11:07:52, Vincent Diepeveen wrote: > >>On October 11, 2002 at 10:38:12, Jeremiah Penery wrote: >> >No it wouldn't. Hsu would not need to do anything other than re-do the design >and submit it to an existing fab shop to produce the chips. It wouldn't be >cheap, >but it wouldn't cost a fortune either. The only cost would be Hsu's salary, >and the fab cost for a run of N chips, where N would probably need to be at >least >1000. I don't claim to have an idea of what the cost would be, as IC >fabrication is >not something I follow closely. But it _would_ be fast as all hell, because >rather than >20mhz they could go 100X faster with no problems at all, and probably do a >better >design since the DB chips had to make concessions for routing and gate delays >that >could be better handled today. So did Hsu say that he thinks that he could run at _100X_ the frequency or is that coming from you? As far as I know, the Belle style move generator that he used cannot be pipelined. (If you think that it could be pipelined, then please elaborate because I sure as hell don't see a way.) So I'm not sure that you would be able to run that at 2 GHz given the amount of combinatorial and routing delay. I expect that it would be difficult or impossible to pipeline the evaluation logic too since at least some of that uses structures similar to the move generation, but I'm not as familiar with that logic. Please note that he used tristate busses for arbitration, so there would be some relatively heavily loaded nets. (Unless he completely changed this logic.) Can somebody ask him about this during the Q and A? Also ask him if he's thought about doing any FPGA work - those Virtex II parts are nice. BTW - You left out the cost of the tools, and I don't know if you would need to buy a library or not. These costs alone would exceed $1M. Keith
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