Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: advantages versus disadvantage P4

Author: Robert Hyatt

Date: 11:04:49 12/12/02

Go up one level in this thread


On December 12, 2002 at 10:15:16, Vincent Diepeveen wrote:

>On December 11, 2002 at 02:34:33, Matt Taylor wrote:
>
>[snip]
>>Eugene's explanation fits, though. I am suprised that Intel did not duplicate
>>the trace cache for both logical CPUs. It's like trying to fit an even bigger
>>peg into an already too small hole...
>>-Matt
>
>Exactly, but the hardware reason to do that is very simply.
>
>They can clock the thing to 3.04Ghz now. 2.8Ghz for the Xeon.
>
>But if you double the L1 data cache size or the trace cache size
>(i will not do a statement what in my eyes is smarter to duplicate
>because you can see my next sentence why) then you have a major other
>problem.
>
>You won't be able to clock it to 3.04Ghz then nor 2.8Ghz for the Xeon.
>
>If you have something small, you can clock it high.
>
>If you have something big like an Itanium2 or the 128KB L1 cache
>of a K7 then you can't clock it that easily to 3.04Ghz.
>
>So the clocking and the size of such important integrated things into
>the procesor is very closely related.
>
>Of course i didn't checkout the P4 manual too well yet
>(it's so big and there are so many manuals), apart from what
>i already posted about it; but i still wonder how they plan
>to replace a spinlock in crafty. I find it a theoretic discussion.
>
>Of course Bob can start using the Huber (abdada or whatever) algorithm
>to parallellize his engine (no locking needed) but i know Bob also posted
>very negative things about that being no real parallel algorithm.
>
>So i wonder how Bob is going to rid of locking within crafty without
>a year or 2 of rewriting crafty by some professional parallel programmer.

First, let's get a few points out of the way.  I _am_ a professional
parallel programmer.  I have written at _least_ 100X as much parallel code
as you have, and, in fact, I spent most of a year explaining parallel
search to you.  I was doing parallel programming in the 1970's.  I had a
parallel search in 1978 at the ACM event, running on a Univac 1100/42
dual-cpu machine.

Second, I am _not_ trying to eliminate spinlocks.  They are necessary and they
can _not_ be eliminated.  I won't explain why, but any book on parallel
programming will give you all the info you need to understand why.

Third, spinlocks are not bad.  The smp_lock in crafty is not bad.  Regardless
of how many times you say it is.  The reason it is not bad is that it is not
used very much.  If I split 2000 times over 3 minutes, I use that smp_lock
2000 times during that 3 minute period.  That is not even measurable as time
used.  it is irrelevant.  It has been irrelevant.  And it will be irrelevant
until I run on a machine with a large (large == 32 or more) number of
processors...

Any time you want to compare programming skills, I'm ready.  And it won't
be much of a contest, IMHO.

Just listening to your rambling makes that point pretty obvious to most
anybody.

Please find another way to discuss things without (a) citing nonsensical
data as fact;  (b) referring to other programs as always inferior to yours;
(c) referring to yourself as the best programmer around.

None of those are true, and stating them over and over will _not_ change
that...


>
>Best regards,
>Vincent



This page took 0 seconds to execute

Last modified: Thu, 15 Apr 21 08:11:13 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.