Author: Vincent Diepeveen
Date: 07:15:16 12/12/02
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On December 11, 2002 at 02:34:33, Matt Taylor wrote: [snip] >Eugene's explanation fits, though. I am suprised that Intel did not duplicate >the trace cache for both logical CPUs. It's like trying to fit an even bigger >peg into an already too small hole... >-Matt Exactly, but the hardware reason to do that is very simply. They can clock the thing to 3.04Ghz now. 2.8Ghz for the Xeon. But if you double the L1 data cache size or the trace cache size (i will not do a statement what in my eyes is smarter to duplicate because you can see my next sentence why) then you have a major other problem. You won't be able to clock it to 3.04Ghz then nor 2.8Ghz for the Xeon. If you have something small, you can clock it high. If you have something big like an Itanium2 or the 128KB L1 cache of a K7 then you can't clock it that easily to 3.04Ghz. So the clocking and the size of such important integrated things into the procesor is very closely related. Of course i didn't checkout the P4 manual too well yet (it's so big and there are so many manuals), apart from what i already posted about it; but i still wonder how they plan to replace a spinlock in crafty. I find it a theoretic discussion. Of course Bob can start using the Huber (abdada or whatever) algorithm to parallellize his engine (no locking needed) but i know Bob also posted very negative things about that being no real parallel algorithm. So i wonder how Bob is going to rid of locking within crafty without a year or 2 of rewriting crafty by some professional parallel programmer. Best regards, Vincent
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