Author: Matt Taylor
Date: 18:16:55 12/13/02
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On December 12, 2002 at 10:15:16, Vincent Diepeveen wrote: >On December 11, 2002 at 02:34:33, Matt Taylor wrote: > >[snip] >>Eugene's explanation fits, though. I am suprised that Intel did not duplicate >>the trace cache for both logical CPUs. It's like trying to fit an even bigger >>peg into an already too small hole... >>-Matt > >Exactly, but the hardware reason to do that is very simply. > >They can clock the thing to 3.04Ghz now. 2.8Ghz for the Xeon. > >But if you double the L1 data cache size or the trace cache size >(i will not do a statement what in my eyes is smarter to duplicate >because you can see my next sentence why) then you have a major other >problem. > >You won't be able to clock it to 3.04Ghz then nor 2.8Ghz for the Xeon. > >If you have something small, you can clock it high. > >If you have something big like an Itanium2 or the 128KB L1 cache >of a K7 then you can't clock it that easily to 3.04Ghz. > >So the clocking and the size of such important integrated things into >the procesor is very closely related. Actually that's not true. There are some 42 million transistors on the P4 Northwood -- more than on Athlon or any IA-32 processor prior to it. Yet it clocks up higher than any competing chips have. The trick isn't to make things simple; it's to split them up. Two independant trace caches would scale fine without adding significant cost to the processor. However, it would impede Intel profit margins because it would require a bit of redesign. -Matt
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