Author: Robert Hyatt
Date: 17:17:26 12/31/02
Go up one level in this thread
On December 31, 2002 at 11:49:31, Vincent Diepeveen wrote: >On December 30, 2002 at 22:32:52, Robert Hyatt wrote: > >>On December 30, 2002 at 20:29:11, Vincent Diepeveen wrote: >> >>>On December 30, 2002 at 19:39:23, Frank Koenig wrote: >>> >>>>Two questions. >>>> >>>>One) Will Intel's HT technology be able to help chess programs above and beyond >>>>just allowing one CPU to appear as two? >>>> >>>>Second) If you are running XP, will HT require XP Pro instead of XP Home to take >>>>advantage of it? >>>> >>>>Thanks, >>>> >>>>Frank >>> >>>For dual machines you need even newer releases of OSes to still get >>>released. >>> >>>However you can profit from it in a very limited way. It's a speedup of >>>18% for DIEP at the latest P4 (3.06Ghz), at older P4s the profit is less >>>(like P4 Xeon 2.8Ghz) and even older P4s the profit is zero or negative. >> >>Any chance you will _ever_ "test before talking"? >> >>The 2.8 xeon has the _same_ SMT core as the PIV/3.06. The _same_ means >>"the same", not "something that is not as good as." > >http://www.realworldtech.com/index.cfm and ask intel designers themselves. In fact, I have. Would you like the name of the Intel Engineer I personally talked to? > >>That is simply a crock statement that is nonsense. From _testing_ on >>my part... > >I see a clear difference in performance. Intel managed to slowly improve SMT >to what it is now. I do not find 18% impressive knowing the chip is already >that much slower than the K7 for me. > >> >>> >>>So it's progressing but the P4 is a processor not really mature enough: >>>too little trace cache and too little datacache: just 1024 quadwords; >> >> >>So? 12K micro-ops. 8kb data. Core-speed L2 cache with 512KB unified >>cache. Seems to work quite well in all the testing I have done. > >If it is in theory simply 2 processors then 11% at older types and 18% at >new P4 3.06ghz is not much and because of the small L1. Also i didn't >figure out yet how big the branch prediction table (BTB) is in the P4 >but it probably isn't so impressive. There are no "older types" of SMT. My xeons produce _exactly_ the same sort of speedup as does the single 3.06 machine we have... > >> >> >>>compare with the 64KB L1 data cache of a K7 which is i guess 16384 >>>doublewords. >> >> >>what is with all the quadword/doubleword nonsense? > >>I think _most_ here can figure out what 64 KB turns into in your favorite >>data size... > >64KB of K7 and just 1024 words of P4. Again, what is with mixing terms? 64KB on K7, 8KB on P4. Although that is not a correct comparison since the P4 has more than 8KB of L1 cache... when you count the trace cache as well. > >The P4 is using 64 bits adressing for the L1 that means just 1024 words. >I prefer personally 16384 words of 32 bits. If you only _understood_ how cache works, you wouldn't dig yourself into these deep, stinky holes. Bus width isn't the issue for how things lay out into cache. Linesize is _the_ critical piece of data as a complete line comes in from memory, not just 32 bits or 64 bits... ALL intel processors access 64 bits at the time from cache. Where have you been??? Every processor since the original pentium had a 64 bit data path. > >However the P4 doesn't deliver 2048 words of 32 bits. It delivers 1024 >words of 64 bits. > ANd there is _no_ difference in the two... >> >> >> >>> >>>It's already having a very small L1 cache and trace cache compared to >>>the L1 of the K7 (128KB) and now you have to divide that by 2 again. >>> >>>So that isn't very positive yet. >>> >>>Let's wait for the future if we can see bigger profits. In which case it >>>gets very interesting of course.
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