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Subject: Re: Tables or Calculation

Author: David Rasmussen

Date: 02:02:44 01/18/03

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On January 18, 2003 at 05:00:16, Matt Taylor wrote:

>
>64-bit shift in something like 3 cycles when count is < 32. Pentium 4 L1 cache
>latency -- 2 clocks. Athlon L1 cache latency -- 3 clocks.
>

I don't understand this

>Bad performance of former indicitive of poor optimization.
>

I don't understand this

/David



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