Author: Matt Taylor
Date: 02:19:14 01/18/03
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On January 18, 2003 at 05:02:44, David Rasmussen wrote: >On January 18, 2003 at 05:00:16, Matt Taylor wrote: > >> >>64-bit shift in something like 3 cycles when count is < 32. Pentium 4 L1 cache >>latency -- 2 clocks. Athlon L1 cache latency -- 3 clocks. > >I don't understand this Yeah, broken English is a bad thing. Here's how it breaks down: Shift form -- 3 cycles Table (Athlon) -- 3 cycles Table (Pentium 4) -- 2 cycles >>Bad performance of former indicitive of poor optimization. > >I don't understand this It means that the compiler is not doing its job. Perhaps there is an optimization switch you have not enabled. Perhaps your inline function is not in a header file where the C compiler can get at it. Perhaps the compiler just flops on 64-bit code. It means basically that something is wrong. There should be almost no difference in speed. -Matt
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