Author: Vincent Diepeveen
Date: 13:50:03 04/14/03
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On April 14, 2003 at 16:35:04, Tom Kerrigan wrote: >On April 14, 2003 at 16:06:57, Vincent Diepeveen wrote: > >>On April 14, 2003 at 15:25:15, Tom Kerrigan wrote: >> >>>On April 13, 2003 at 22:58:48, Jeremiah Penery wrote: >>> >>>>>I bet intel will call P4-Prescott to be SMT too instead of CMP. But do you >>>>>really believe it's SMT? >>>> >>>>Um, yes. >>> >>>Heh. Absolutely. >>> >>>Look at the pictures of the die. >>> >>>Do you see 2 CPUs? >> >>>I don't. >> >>Look again. 2 rapid execution engines (cpu's) with each their own 16KB L1 cache: >> >>http://www.chip-architect.com/news/2003_03_06_Looking_at_Intels_Prescott.html > >Ha, you think rapid execution engines are CPUs? > >Then what is all that other stuff on the chip, besides the rapid execution units >and the L2 cache? >Filler? Useless crap i hope or next prescott will dick us again in performance. P4 already is dead slow for its price and knowing that SMT hardly can get used as it improves nps too little. Seeing Trace cache is so big it is understandable they just put 1 copy on the chip of it, but i really regret it for DIEP. Decoding 1 instruction a clock sucks ass. Even my sister can do that faster ;) Any notion that is improved at prescott? Anyway that L1 cache really is nice to have for both chips. 4 instructions a clock is a big improvement and the L1 is improved to 16KB and the tracecach to 16k. So that's at least some progress at important points for DIEP. 8KB L1 cache really was too little. And that 4 instructions a clock might be an interesting factor. How much hyperthreading gives for prescott we will have to wait and see of course. It's looking good though. It's like that first itanic experiment. itanic1 was dead slow. But McKinley rocks the boat. At the same clock like itanic1 it is 3 times faster exactly! That's how i see the P4 too. Apart from somewhere 2004 we might expect prescott in the shops at real high clock rates. >-Tom Vincent
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