Author: Vincent Diepeveen
Date: 06:01:02 06/30/03
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On June 30, 2003 at 00:09:06, Anthony Cozzie wrote: >>That program is so outdated technical seen that it still more or less fits in >>the L1 cache, nowadays called trace cache. > >I think you might understand a trace cache, but that statement is seriously off. > A trace cache is not a synonym for a L1 cache. P4 doesn't have a L1 instruction cache instead it has a trace cache which doesn't hold instructions but decoded instructions instead (so they do not need to decode them before executing, in itself a genious idea). The size is not the big problem of it. the problem is that if your program is a lot bigger than that cache, that decoding to the trace cache can be done with at most 1 instruction a clock. C programs in general execute at more than 1 instruction a clock. Chessprograms are *very* well optimized. This is probably why the new P4 has a slightly bigger trace cache. from 12K they go to 16K instructions. So tracecache *is* the equivalent here of L1 instruction cache with the K7. So instructions that need to get decoded first can execute at most at 1 instruction a clock. Stuff inside the tracecache can get executed like it can get executed at the K7, with 3 instructions a clock. Therefore a small program that fits within the trace cache and doesn't suffer from penalties from branches too much, will be executing very quickly at the P4. It is trivial that chessprograms in general get more and more complex now and that this design of the processor is very BAD for the speedup that SMT potentially can deliver to you. > >>Of course the marketing department never told you fritz doesn't know the diff >>between a bishop and a knight. > >that made my day. > >anthony > >go x86-64!!
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