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Subject: Re: There is huge potential to improve further

Author: Vincent Diepeveen

Date: 09:54:49 07/09/03

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On July 09, 2003 at 07:02:01, Gerd Isenberg wrote:

>
>Current Opterons use so called "DirectPath Double" decode type for most SSE/SSE2
>128-bit instructions, internally they do two 64-byte macroops. But AMD already
>mentioned "Future" Processors with 128-bit "DirectPath" SSE/SSE2 instructions:
>(Software Optimization Guide for AMD Athlon™ 64 and AMD Opteron™, Chapter 9
>Optimizing with SIMD Instructions).
>
>That's a boost to floating point and also SIMD integer algorithms like
>KoggeStone. But when will it be?
>
>Like Athlon, Bitscan (bsf, bsr) and Bittest (btx) instructions are still Vector
>path pipe-blockers (but of course 64-bit). Same for moving data between gp- and
>xmm- or mmx- registers.
>
>Still no popcount and instructions for "reverse" arithmetics (radd, rsub, rneg),
>where the overflow passes from high to low :-(
>
>Cheers,
>Gerd

And already 1562 in specint with crafty using 64 bits crafty.

Please compare what the opteron can do for crafty with the itanium2 and you'll
know which is the better CPU in the future.

Itanium2 doesn't have bsf/bsr even if i understand well. You need to do it
indirectly at the itanium2!!!!




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