Author: Vincent Diepeveen
Date: 09:36:28 08/29/03
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On August 29, 2003 at 08:49:09, Dezhi Zhao wrote: >On August 28, 2003 at 11:45:35, Robert Hyatt wrote: > >>I'm not talking about write-through. I am talking about write-back. Once >>you modify a line of cache, that line of cache _is_ going to be written back >>to memory. When is hard to predict, but before it is replaced by another cache >>line, it _will_ be written back. So you write one byte to cache on a PIV, you >>are going to dump 128 bytes back to memory at some point. With only 4096 lines >>of cache, it won't be long before that happens... And there is no way to >>prevent it. >> > >Are the cache line sizes of L1 and L2 are different for P4? I was always >thinking of a L1 load or store is 64 bytes. yes they are way smaller than 64 bytes. Only to the slow memory it is 128 bytes at the P4 and 64 bytes at the K7. Opteron i don't know yet. You can look in the processor manuals how many bytes each L cache can get at a time. It's different for each processor seemingly. A lot of criticism was there not too long ago, about the new transmeta chip which is getting some big size at a time. 128 bytes or something. Great for DSP but probably not so great for computerchess :) Best regards, Vincent
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