Author: Tom Kerrigan
Date: 17:56:05 03/05/00
Go up one level in this thread
On March 05, 2000 at 10:19:59, Robert Hyatt wrote: >>I don't see why you want to bring the cache into this, if you just want to >>compare the cores. (Which I do.) >two reasons. (1) if a program fits totally in cache, you are testing one >aspect of the cpu. If the program doesn't fit into cache, you add memory >bandwidth and cache miss handling into the equation. (2) "core" speed is >only important for a program that fits completely in cache. I am not aware This is straying from my original question. I'm not trying to prove that the P5 is better than the P6, because it isn't. I just want to know what kind of concrete performance improvement we are getting from these nifty new microprocessor features. >>>Which means no register jams occur in the program. For more complex programs, >>>the renaming logic in the P6 avoids many register jams/spills and does much >>>better keeping both pipes filled. >>Do you have any proof of this? >This is a trivial thing to consider. If you have 1 register, try to figure >out a way to keep 2 instruction pipes busy, since both can't update that one >register in one cycle, nor can one update while the other reads. If you have Yes, I know exactly how all of this stuff works. I'm still only interested in the concrete improvement (and not necessarily for the x86). I thought I made this extremely clear a few posts ago. If you don't have any actual data, I'm a little confused as to why you're replying to my posts. -Tom
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