Author: Vincent Lejeune
Date: 18:22:09 09/28/00
Go up one level in this thread
>>>>>So a single lookup in memory is in its most realistic case: >>>>> 10ns x 11T = 110 clocks. >>>>> >>>>>You can do a lot in 110 clocks! >>>>> >>>>>If that gets suddenly down to less as 20 clocks, then >>>>>it's clear that this rocks bigtime. >>>>> >>>>>considering the huge number of tables in my program which all together >>>>>eat hundreds of kilobytes of RAM, i'm estimating that speedup *might* >>>>>be like 20% or so in the middlegame for DIEP. >>>>> >>>>>However programs that are very fast and are basically wasting their system >>>>>time at hashtables might profit even more. I wouldn't be amazed by a 2 fold >>>>>speedup for certain programs. >>>>> >>>>>That's what EDO ram to SDRAM did for my draughtsprogram at least... >> >>I actually tried an RDRAM machine recently. I ran my chess program benchmark >>(WAC at 1s/posn) on a P3/933 + PC800 and got 1060 knps. I have a P3/933 with >>SDRAM at home. On that system I get 1083 knps. >> >>So, at least with my program, SDRAM is slightly better. I suspect that SDRAM >>will actually be a whole lot better if your program is at all memory speed >>bound. Mine isn't apparently: when I set the memory to run at 100 MHz instead >>of 133 MHz (which I can do independent of the FSB speed with the motherboard >>I'm using) I get 1066 knps--which is still faster than the RDRAM result... >>-Dan. > >I'm amazed! > >What SDRAM133 do you have at home, 2-2-2, 2-3-3 or 3-3-3? >the difference between 2-2-2 (which is the fastest) and 3-3-3 should >be a bit less as 10% for latency. > >What chipset did the machine have where you tested the rdram at and >how many banks of RIMMS did it have? > >Thanks in advance, >Vincent And new techonology are comming in this area : http://www.aceshardware.com/Spades/list_news.php?category=HARDWARE -Low latency DDR-II will be based on EDRAM- ...E-DDR II performs, according to independent studies of IBM and the university of Maryland up to 22% better in SpecInt than DDR-II!... The beauty about the EDRAM concept is that it adds very little SRAM and thus die space to the chip, to be more exact only 1.4%!. Those SRAM buffers contain the row data, and the controller can read those buffers instead of the sense amps. While the SRAM buffers are read, the sense amps are free for precharge and refresh operations. In other words, those SRAM buffers can eliminate latencies like the precharge latency.
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.