Author: David Blackman
Date: 18:31:07 02/10/98
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On February 10, 1998 at 15:13:08, David Fotland wrote: >On February 10, 1998 at 09:22:13, Robert Hyatt wrote: >>As I said, the *single* most important thing to do on modern micro- >>processor architectures is to do everything possible to ensure cache >>hits. *every* miss is expensive. Every hit is basically free. [snip] > Expect system early next century to waste more than 100 >instruction times on each cache miss. Also expect the cache line >size to increase, so more data is brought in with each miss. > >David Fotland 100 instruction times for a cache miss is fairly common right now, especially if there is a TLB miss at the same time, and there often is. There are some signs of hope that system designers are trying to improve latency, so maybe they won't get much worse than 100 instructions/miss for the next few years. Example: 200MHz pentium peaks at 2 instructions per clock or 2.5ns per instruction, and typically 4 to 8 ns. Typical measured latency to main memory is 200ns to 800ns depending on how good the motherboard is, and whether there is a TLB miss at the same time.
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