Author: Ian Osgood
Date: 10:32:46 09/20/01
Go up one level in this thread
On September 19, 2001 at 22:30:58, Christophe Theron wrote: >I think it is possible to find (or write) a C compiler for this Forth chip. > >A few years ago I have created for a commercial company a language which >resembles Basic. It was composed of a compiler, which produced P-Code, and an >interpreter, which executed the P-Code. > >The P-Code was based on a virtual stack machine that looks a little bit like >what this Forth chip implements. Actually it is quite "easy" (well everything is >relative) to compile a high level language if your goal is simply to produce >code that can be executed by a stack machine. > >Naturally, optimizing the produced code is another story, but I don't see why it >would be more complex than for a "classic" processor. Yes, it was mentioned that Forth is very like p-code, and that writing a Forth back-end is easier in compilers which are simpler than gcc. In fact, there is a university textbook whose main excercise is to create the Forth backend to a simple compiler. >Looking at the specs of the Forth chip, I see other problems: >* 18 bits address bus => 256K words max address space (a little bit more than >512Kb). >* 18 bits words: this is completely non-standard. I remember an old Multics >computer at my university using 18 bits words, but it was a prehistoric monster. >You would have problems using this word size with standard C (at least forget >about using standard C libraries). Indeed. Remember, this chip was designed by the inventor of Forth, to some extent for his own use as a Forth programmer and systems solution provider. "C? Who needs it? I can do anything I would want to do in machine Forth." :) >* the return stack is limited to 16 levels: you would probably have to bypass >this stack and create your own (or to add expensive logic around the existing >stack management) to avoid return stack overflows. Perhaps they envisioned some sort of stack paging scheme: interrupt on stack overflow or underflow which pages in different portions of a larger stack backed up in RAM. Or perhaps they are aiming at simpler applications which don't require large amounts of stack, where a microcontroller or DSP would normally be used. > >The idea of this asynchronous processor is extremely attractive. No clock. Just >design it in a smart way and everything is executed as fast as your transistors >can switch. Hard to do anything faster on a silicon wafer. > >Actually it looks like it has a clock: a series of 14 Nand gates are used to >create a delay, and an instruction is fetched each time the signal has passed >these 14 gates. So all the instructions must be executed in less time than 14 >"Nand switches". > >There are only 27 instructions, so they can all be coded on 5 bits. Each 18 bits >word contains 3 instructions. > >I recommend reading the specs of this chip if you like beautiful technology. >It's so incredibly well designed that at first I thought it was a joke. > > > > Christophe I agree. It is refreshing to see someone (and I mean "one"! How many other processors have been designed entirely by one individual?) trying for a minimal CPU design to achieve speed. Everyone else throws large teams at the problem, coming up with huge seas of transistors to implement hundreds of instructions, complex pipelines, branch prediction, reordering, backward compatability etc. etc. Though I guess this is more of a microcontroller than a full microprocessor. Ian
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