Author: Dan Newman
Date: 10:30:59 01/11/02
Go up one level in this thread
On January 10, 2002 at 17:09:24, Tom Kerrigan wrote: >On January 10, 2002 at 05:53:25, Gian-Carlo Pascutto wrote: > >>On January 10, 2002 at 05:07:37, Tom Kerrigan wrote: >>>It's the first x86 chip to have a trace cache. >>Hardly impressive, crippled as implemented, minor extensions of >>a known theme. > >What about the P4's trace cache is crippled? And what is it a minor extension >of? Trace caches, AFAIK, have only been used in extremely obscure VLIW computers >that existed more than a decade ago. > >>>Its branch predictor is probably the best ever made >>>by anybody. >>Again, minor extension of a known theme. They also had no >>choice given the pipeline. > >If your job was to make branch predictors, I don't think you'd be saying that. >You might as well say the entire P4 design is a minor extension of a known >theme, the theme being microprocessors. > >>>It has SMT logic (although not enabled currently). >>Nothing new in that, and as you say, it's not even enabled. > >How is that nothing new?? What other processors have SMT, besides that one >super-obscure mainframe processor that isn't being made anymore and that I >forgot the name of? > That would be the Trace Multiflow. It was in a class of computer known as "super-minicomputer". I got to play with one for about a year or two at the lab where I worked. IIRC, the one we had had an instruction word 256 bits wide and contained 5 instructions. We typically got about 1/4 the speed of our much more expensive Cray XMP. It would also run code that was unvectorizable at vector speeds (which was why it was 1/4 of a Cray). Its instruction set was very much in the RISC camp with all the instruction scheduling done by the compiler (including code to undo work done on the wrong branch). The guys at Multiflow used to come out to fix things by soldering jumpers on the enormous circuit board modules (probably 3x3 feet by 1.5 inches). It was a work in progress. Unfortunately (for Multiflow), by a couple of years later, it made more sense to use multiple workstations like the RS6000 (which is what our theoretical group switched to), and the Trace was mothballed. I think things were moving too fast for Multiflow to keep up. Building a large machine like that creates a lot of inertia. -Dan. >>>Besides, how do you know it's even possible to make a smarter chip than the P3? >>Even Intel seems to think so given the Itanium. The first benchmarks >>weren't exactly encouraging though. I hope that improves with the next >>generations soon. > >The Itanium doesn't get higher ILP from x86 code. Apples and oranges. > >-Tom
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