Author: Robert Hyatt
Date: 12:18:45 07/12/98
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On July 12, 1998 at 15:08:53, Tom Kerrigan wrote: >>>Remember, the PII L2 cache *always* runs at half the core clock speed. >>The PII doesn't always run at 1/2. That's what the PII/Xeon is all about, > >The PII doesn't always run at 1/2 what? Seeing as the statement was written to >contradict mine, I assume you meant the L2 cache doesn't always run at 1/2 the >core clock speed, which is wrong. Why haven't you figured this out yet? > No it is *not* wrong. Simply go pick up a reference for the PII/xeon, and you might be amazed to discover that (a) it is still called a Pentium II, and (b) the cache runs at cpu speed. The processor was announced a week before you made your wrong statement. As I said, *all* PII's do not run the cache at 1/2 cpu speed. Understand now??? >You were also relying on your misstatement to explain why the PII/400 doesn't go >nearly as fast as it "should," so perhaps you should think of a better argument. > My statement still stands. A PII/200 is slower than my P6/200. A PII/233 is slower than my P6/200, but not by a lot. A PII/300 is exactly 1.41 times faster than my P6/200. Since the *only* difference between a pentium II running at 200mhz (yes they exist, although they are underclocked for some unknown reason) is the L2 cache speed, it is pretty obvious that the cache is causing the lack of performance that *I* see. I also have a well-known matrix multiply benchmark that uses a 40mb array, and it scales perfectly from the P6/200 thru the PII/400, because *it does not use cache*. It was specifically written to blow cache out and measure processor/memory bandwidth rather than processor/cache bandwidth. So, I have no idea what you are rambling on about. But please don't hit me with the argument that "I work at Intel and I know what I am talking about." That argument doesn't cut it. I've been working with the Spec folks for a year on the Crafty deal, and have seen more than enough spec figures to know how all the intel chips perform, both on cache-friendly and cache-unfriendly applications. My statement is correct and was correct. Whether there was room to misinterpret it, I don't know. But we can go back to the original statement you quoted above, and that's provable "all PII's do *not* run their cache at cpu/2 clock speed, as of about one year ago technically (when the first xeon was being tested) or as of about 2 weeks ago practically (when the xeon was publicly announced.) Your statement was made after xeon was public. And it's still wrong. >-Tom
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