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Subject: Re: Who can update about new 64 bits chip?

Author: Vincent Diepeveen

Date: 10:04:09 08/25/02

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On August 25, 2002 at 12:52:38, Dan Andersson wrote:

>>
>>I need to note that the difference between 150ns and 80ns is nearly
>>a factor 2, if that's not *considerable slower* then what is considerable
>>slower? Memory that gets 2 times slower, that's a *big* slowdown.
>>
>Two hops or more will happen on systems with *many* CPUs. And the average cost
>will be something like 1/n*80+a/n*115+b/n*150 ns (1+a+b=n). So the average would
>lie in the ballpark of 120 ns on an average system (and it will be less than 190
>ns for a huge system). Thats ca 50% more than a normal memory access. Not to
>shabby. Thus algoritmic alterations could be possible that ammortize the cost of
>that extra 50%. I.e. Multi Probe, PV length two or more, et.c.But we will have
>to see the actual performance of the chip to be sure.
>MvH Dan Andersson

please don't quote theoretic numbers. a chess program is not a theoretic
'read only a single stream' program.

A chessprogram is both writing and reading. That's not going to be 190ns
at all.

I'm not interested in a dual of course. I'm not interested in a 4
processor hammer even. 8 processor hammer is more interesting though.

SGI has about 1200 ns for 128 processors (each node = dual) see:

http://techpubs.sgi.com/library/tpl/cgi-bin/getdoc.cgi?coll=0650&db=bks&srch=&fname=/SGI_Developer/OrOn2_PfTune/sgi_html/ch01.html

That's a read LATENCY. Just as interesting is of course the costs
of a write.




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