Author: Jesper Antonsson
Date: 10:15:53 10/27/02
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On October 27, 2002 at 09:55:32, Bob Durrett wrote: >Based on your prediction, how soon before microscopic microprocessors become >available? [Assume many on a chip] Well, good question. It's obvious that the current crop of microprocessors aren't optimized for chess, that use pretty standard integer arithmetic. Instead, a lot of chip real estate is devoted to SIMD solutions and such to make Quake run faster. Granted, more cache, better branch prediction, superscalarity, deeper pipelines do benefit chess programs, but I think it could be made much better if one focused on chess. Unfortunately, Intel and AMD won't focus on chess. :-) But lets see: P4 0.13um 55 MT (million transistors). P3 0.18um 28 MT P2 0.25um 7.5 MT P2 0.35um 7.5 MT PMMX 0.35um 4.5 MT P 0.6um 3.3 MT 486 0.8um 1.2 MT 386DX 1.5um 0.275 MT Now it's just maths. The number of transistors grows by the inverse square of the line width. (To prove the point, 1.5um and 275KT would in theory give us around (1.5/0.13)^2 * 275K = 37M at a .13um process, which is quite close to 55 MT.) Theoretically, we could put 200 386DX processors in the same space as one P4, and they could, with modifications, be made to run with current clock frequencies. In 2017, following Moore's law of transistor doubling every 18 months, we could put 1024 P4 in the same area as one P4 occupies today, or 200,000 386DX. Of course, neither of those numbers may be pratical for different reasons, and some transistors will have to be used to "glue" the processors together. We'll just have to see if Intel&Co goes for more Quake performance on a serial processor, or if parallelism on a chip becomes mainstream. It all depends on where the money is. :-) But perhaps there will be even more different architectures to serve different purposes in the future.
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