Author: Tom Kerrigan
Date: 05:09:23 02/07/03
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On February 07, 2003 at 03:10:46, Matt Taylor wrote: >There is another subtle difference, too; IA-64 is heavily optimized in software >whereas IA-32 is heavily optimized in hardware. In IA-64 it is possible to >achieve rates closer to the theoretical 6 instructions per clock than it is on >IA-32. Possibly only because it runs at a much lower clock speed. >The IA-64 is probably extremely nice to compute with (6 MB L2 cache!!) if you Sort of. A 3GHz P4 outscores a 900MHz McKinely by 67% at SPECint2k, which is what's important for computer chess. McKinley is good at SPECfp2k. Maybe that's what you're referring to. >Athlon64 will support all of these instructions. Yes, it is a waste when >significant portions of the CPU core are dedicated to MMX/SSE and no compiler >can generate MMX/SSE code, but an astute assembly programmer can write code for The Intel compiler can generate SSE2 (instead of x87) for floating point calculations. I believe gcc has library functions that make use of MMX. I wouldn't say MMX or SSE uses significant portions of the CPU core, relatively speaking. The difference between a Pentium and a Pentium MMX is ~1M transistors, and probably most of those were devoted to doubling the L1 cache sizes, not to MMX functionality. The difference between the Pentium 2 and the Pentium 3 (with SSE) is ~2M transistors. I guess you can decide for yourself if these numbers are significant. -Tom
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