Computer Chess Club Archives




Subject: Re: Introducing "No-Moore's Law"

Author: Tom Kerrigan

Date: 15:18:08 02/28/03

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Look at Celerons. They're sold at lower clock speeds than P4s, except they're
P4s with L2 cache defects. Which is the simplest explanation:

1) P4s with L2 cache defects also happen to be the slower P4s somehow
2) Intel doesn't want Celerons competing with high-end P4s


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