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Subject: Re: Introducing "No-Moore's Law"

Author: Robert Hyatt

Date: 20:42:53 02/28/03

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On February 28, 2003 at 18:18:08, Tom Kerrigan wrote:

>Look at Celerons. They're sold at lower clock speeds than P4s, except they're
>P4s with L2 cache defects. Which is the simplest explanation:
>
>1) P4s with L2 cache defects also happen to be the slower P4s somehow
>2) Intel doesn't want Celerons competing with high-end P4s
>
>-Tom


Once again, we have been discussing _high-end_ chips.  Not low-end chips.

IE celerons were once pentiums with defective cache, and even pentiums with
_disabled_ cache.  Just like 486sx chips were 486's with (originally) defective
math pipes, but later were 486's with disabled pipes.  That is taking a part off
a current fab line and re-marking it to fill a low-end niche.  Sometimes that is
more cost-effective than building more of the original.

This has been the case for 30+ years.  Back in the 1970's the same thing went
on in the calculator chip market.  And a whole group of "hackers" sprang up
showing how to add new buttons to your calculator to access more advanced things
like trig, memory, etc, that were not accessible by the keys on the front.  It
was cheaper to make a run of one kind of chip and when the demand for the best
chips is less than production, siphon the rest off and sell them cheaper...  in
reduced functionality calculators.

But I don't see this on the top end.  IE someone has a fab line that can produce
4ghz processors, but they only produce 3ghz parts for whatever reason and
_never_ ship the 4ghz parts until the competition catches up to them.  That
doesn't make financial sense.



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