Author: Matt Taylor
Date: 09:46:15 03/19/03
Go up one level in this thread
On March 18, 2003 at 23:18:15, Robert Hyatt wrote: >On March 18, 2003 at 21:32:16, Matt Taylor wrote: > >>On March 18, 2003 at 16:41:03, Robert Hyatt wrote: >> >>>On March 18, 2003 at 15:42:56, Aaron Gordon wrote: >>> >>>>On March 18, 2003 at 10:12:56, Robert Hyatt wrote: >>>> >>>>>On March 18, 2003 at 00:24:01, Aaron Gordon wrote: >>>>> >>>>>>On March 18, 2003 at 00:01:44, Robert Hyatt wrote: >>>>>> >>>>>>>On March 17, 2003 at 22:59:30, Aaron Gordon wrote: >>>>>>> >>>>>>>>On March 17, 2003 at 18:47:27, Eugene Nalimov wrote: >>>>>>>> >>>>>>>>>I just run the experiment. I used 2 otherwise identical 64-bit systems, one with >>>>>>>>>3Mb of L3 cache, other with 1.5Mb. Machine with bigger cache run Crafty's >>>>>>>>>"bench" comman 12% faster (1 CPU). >>>>>>>>> >>>>>>>>>That means that >>>>>>>>>(1) Crafty's working set don't fit into 1.5Mb, >>>>>>>>>(2) For systems with cache 1.5Mb or less (i.e. for almost all x86 systems) for >>>>>>>>>Crafty memory speed matter. >>>>>>>>> >>>>>>>>>Thanks, >>>>>>>>>Eugene >>>>>>>> >>>>>>>>Those types of systems aren't what people normally use. Most people here have a >>>>>>>>Pentium 3, Athlon, Pentium 4, etc. Here is something I found with Crafty. >>>>>>>> >>>>>>>>Using the Nforce2 chipset I'm able to run the ram at speeds from 50% up to 200% >>>>>>>>(100% being synchronous) of the fsb speed. I tested 200MHz FSB (400DDR) with >>>>>>>>200MHz memory (400DDR) and 200fsb with 100MHz memory (200DDR). >>>>>>>>The difference between ~1.6gb/s memory and ~3.2gb/s memory with craftys 'bench' >>>>>>>>command was 0.14%. Yes, about one seventh of one percent. >>>>>>> >>>>>>>That might well suggest _another_ bottleneck in that particular machine.... >>>>>> >>>>>>Another bottleneck? What was the original one? >>>>> >>>>> >>>>>The original one was assumed to be bus speed. That's where I entered the >>>>>discussion. But bus speed is not the _only_ issue that can cause problems >>>>>here. >>>>> >>>>>Lack of interleaving is another. >>>> >>>>All modern single cpu computers have 4 way/4 bank memory interleaving. Even my >>>>old dual Celeron box has 4 bank/4 way interleaving... >>> >>> >>>Most do _not_ support interleaving. I'm _specifically_ talking about four banks >>>to do >>>four consecutive 8-byte reads at once, then you want for the initial 120ns >>>delay, and grab >>>the first 8 bytes, followed by the remaining 24 bytes on the next 3 bus cycles. >>>Repeat to >>>fill a cache line. >>> >>>I am not aware of _any_ single-cpu machines with interleaving. You have to have >>>a machine >>>with 4 banks, with 4 SIMMS/DIMMS/etc as well. >>> >>>Give me a model number for your celeron and I'll look. But Unless you have four >>>separate >>>DIMMS in it, it ain't doing 4-way interleaving. >> >>http://www.msi.com.tw/program/products/mainboard/mbd/pro_mbd_detail.php?UID=398&MODEL=MS-6570 >> >>"Supports 600MHz up to Athlon™ XP 2700+ processor or higher" >>"Support Dual channel PC3200/2700/2100/1600 DDR SDRAMs" >> >>The fact that it uses multiple banks is still significant because you can do 2 >>random accesses concurrently for a lower average realized latency. I don't know >>if this is how the chipset handles it, but they're obviously taking advantage of >>it somehow. >> >>-Matt > > >OK... perhaps you and Aaron are both correct here. I don't really know whether interleaving is common, but I'm saying that my nForce 2 board has it. As for the bit about multiple banks, that's really just a guess that I threw out. I'm supposing; I don't actually know whether that's true. >The purpose of interleaving for duals/quads is to unbusy the memory unit >as quickly as possible. IE my quad has four banks of DIMMS. So in a twisted >way, that _could_ be considered 8-way interleaving I suppose, although the >machine claims to have four banks and 4-way interleaving. > >So, if we call DIMM 2-way, then 4-way is 4X that, which is a confusing way >of reporting things. A DIMM clearly can't transfer 16 bytes in a single cycle >as there isn't that many pins on the thing, unless my eyes were bad when I >plugged 'em in to my quad and dual. > >So I guess what I should say is that whatever a normal PC is doing, my quad >is dong 4x that in terms of interleaving. Not all are. I have a DIMM that only uses 1 bank. SDRAM uses 168-pins, so it is plausible that it could transfer 128 bits in a cycle, but IIRC it doesn't have that many data pins. Same case with DDR. All the memory terms are confusing because the marketting people confused them. You have "quad-pumped" and "interleaved" and "dual-channel." It's worse since marketting people have no concept of clocking, so they make silly claims about a 333 MHz FSB on Athlon and similar claims about RDRAM. Anyway, the point of my little rant is to simply say that interleaving != interleaving. Depending on who you ask, it could mean any number of things. I would not trust a motherboard description because marketting people will say anything that sells. -Matt
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