Author: Robert Hyatt
Date: 19:55:41 03/19/03
Go up one level in this thread
On March 19, 2003 at 16:04:04, Matt Taylor wrote: >On March 19, 2003 at 14:04:27, Robert Hyatt wrote: > >>On March 19, 2003 at 12:58:07, Matt Taylor wrote: >> >>>On March 18, 2003 at 23:11:35, Robert Hyatt wrote: >>> >>>>On March 18, 2003 at 20:22:33, Jeremiah Penery wrote: >>>> >>>>>This exact discussion has taken place here at least twice before. I'm not sure >>>>>why Bob persists with his 120ns number, but no amount of convincing or data is >>>>>going to change his mind. >>>> >>>> >>>>Would you care to post some _exact_ data that disproves 120ns? Did you see >>>>Matt's number in the post parallel to yours? Using current DDR ram speeds? >>>> >>>>So your "no amount of convincing" leaves me cold. "no amount of data" has yet >>>>been presented to show any machine with < 100ns latency. Feel free to disprove >>>>it but post your code. Any old sloppy C code won't do, the code has to be >>>>written to test latency, not prefetching or cache reuse. >>> >>>I used registered DDR which is slower, and being on SMP it will also be slower. >>>It is conceivable that someone has ~100 ns latency. I'll try running the >>>benchmark later on my nForce 2 board w/pc2100 CL 2.5 non-registered ram. >>> >>>-Matt >> >> >>Actually I believe all our duals use registered DDR ram also, which probably >>explains those near-150 ns numbers I have seen for the DDR machines. >> 150 is way non-impressive. > >From what I understand, registered ram uses an SRAM cache. They copy the row >into the cache and then close the row. This is supposed to conserve power, and >they claim it makes it "more stable." > >-Matt That was my interpretation as well. However it seems that perhaps they dump the entire N bytes they need _before_ clocking it onto the bus, which seems odd and stretches latency for no real gain I can grasp. That might account for the extra 20ns I am seeing on my DDRAM boxes.
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