Author: Vincent Diepeveen
Date: 09:29:18 07/02/03
Go up one level in this thread
On July 01, 2003 at 16:02:40, Robert Hyatt wrote: >On July 01, 2003 at 13:20:32, Tom Kerrigan wrote: > >>On July 01, 2003 at 11:57:58, Robert Hyatt wrote: >> >>>On June 30, 2003 at 21:03:30, Tom Kerrigan wrote: >>> >>>>On June 29, 2003 at 23:50:11, Robert Hyatt wrote: >>>> >>>>>On June 29, 2003 at 06:35:02, Tony Werten wrote: >>>>> >>>>>>On June 28, 2003 at 14:23:50, Robert Hyatt wrote: >>>>>> >>>>>>>On June 28, 2003 at 12:12:15, Jay Urbanski wrote: >>>>>>> >>>>>>>>On June 28, 2003 at 10:33:45, Robert Hyatt wrote: >>>>>>>> >>>>>>>>>Those are not true 64 bit processors. Supposedly 32 bit stuff runs just >>>>>>>>>fine on them, but they have 64 bit extensions. >>>>>>>> >>>>>>>>How is Opteron not a true 64-bit processor? >>>>>>> >>>>>>> >>>>>>>Because it executes 32 bit instructions _also_. >>>>>> >>>>>>P4 and AMD also execute 16-bit instructions, so they are 16 bit processors ? >>>>> >>>>>Not pure 16 bit no. Not pure 32 either. >>>>> >>>>>Check out "Cray" for a better example of a pure architecture. >>>>> >>>>>All math is 64 bits. All address arithmetic is 32 bits. Different >>>>>instructions, functional units, and registers for each. No kludges about >>>>>gating 32 bits with 32 high-end zeroes and that kind of stuff. >>>>> >>>>>But in the case of opteron, at least at first look, it appears to be a 32 >>>>>bit machine with 64 bit instructions layered on top. >>>> >>>>Are you kidding me? >>>> >>>>The "bitiness" is the width of a chip's datapath, right? >>> >>>Yes. But there is more. A chip made to do 64 bit operations as its _normal_ >>>mode of functioning is a 64 bit chip. A chip that does 32 bit operations >>>normally, with 64 bit add-ons, is not really a _full_ 64 bit chip. >>> >>>That was, and is, my point. >> >>How do you figure that the Opteron/PA-RISC/UltraSPARC/MIPS/POWER do not do >>64-bit operations as their "normal" mode of functioning? They have 64 bit >>registers and the values in those registers are communicated over 64 bit busses >>to 64 bit buffers and 64 bit latches and 64 bit ALUs. How can you possibly get >>more 64 bit than that? Just because all of this hardware _can_ be utilized to >>also execute 32 bit instructions (the same way a chip does a "2 bit instruction" >>when you calculate the sum of 1 + 1) doesn't mean it's not a 64 bit chip. > >No, but it _very likely_ means that the design has some trade-offs to make the >32 bit stuff work. IE it is simply easier to do everything in 64 bit mode >rather than having to special-case some 32 bit stuff using the same registers, >as then there are all the normal sign-bit problems, to name just one issue. > >Note that I didn't say that the opteron was trash. Far from it. I simply said >that I doubt it is a pure 64-bit processor, since it was first designed to be >compatible with the X86 (poor) architecture, and then had 64 bit supported >added on top. > >The X86 architecture itself is bad enough. > > >> >>Conceptually, all of these ISAs can be viewed as "add-ons" or "extensions" if >>you're going to make a PowerPoint block diagram, but that has no bearing on the >>design of the processor. All of these chips can decode 32 or 64 bit instructions >>(with mostly the same logic, in fact) equally fast. Saying "add on" makes it >>sound like the 64 bit instructions must first be translated to 32 bit >>instructions or something. > >Not what I implied. Having to execute instructions designed for 32 bits >requires some concessions that a pure 64 bit machine doesn't have to deal >with. Again, the Cray is the perfect example, in that even though it does >both 32 and 64 bit stuff, 32 bit for addresses only, and 64 bits for math >only, everything is _clean_ and there are no worries about doing any 32 bit >stuff on the 64 bit functional units, etc. > > > > >> >>>>The Athlon and Pentium quite obviously have a 32 bit datapath so they are 32-bit >>>>chips. The Opteron has a 64 bit datapath so it's a 64-bit chip. >>>> >>>>I don't know what you mean by "64 bit instructions layered on top." >>>> >>>>-Tom >>> >>>It runs X86 natively. That is a 32 bit instruction set. >> >>So does IA64, although you apparently didn't realize this. > >No I didn't, although I am not an IA64 person. However, how does a VLIW >architecture execute mov al,x type instructions? If the hardware can do >that it would be interesting. If software has to do some translation then >it would be a kludge like the alpha/vax solution. > >But if you can throw in X86 instructions into the mix of normal Itanium >instructions, that would suggest more than just a kludge. > >> >>-Tom It is incredible to see how so much nonsense can be written by you Bob, just because you are too stubborn to admit that the opteron is a 64 bits chip. It even has its own x86-64 bits instruction set for that. The sucking itanium-madison 1.3Ghz chips are also 64 bits depite that they are downwards compatible to execute IA-8 bits code. No one calls that a 8 bits chip! Though it is not worth more than 8 pennies. It cannot execute correctly scientific software at all. All the big benches run at it currently produce wrong results after long runs. Of course most benches like specint/specfpu do not verify that a result is obtained correctly. Yet it is not called a buggy cpu it is not called a 8 bits cpu it is not called a 32 bits cpu, but it is a 64 bits cpu. Perhaps let's try the approach most people use with childs: The opteron is a 64 bits chip. Period. Best regards, Vincent
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