Author: Slater Wold
Date: 18:27:10 08/07/03
Go up one level in this thread
On August 07, 2003 at 12:26:12, Matthew Hull wrote: >On August 06, 2003 at 17:30:24, Slater Wold wrote: > >>I clicked the "Call me now" option, entered my name & number, and 20 seconds >>later someone from IBM called me. > >Cool. > >> >>Of course she couldn't answer my question, but I did get an answer: >> >>"For high performance computing (HPC) customers, the p690 has an HPC option that >>can provide increased memory & I/O bandwidth per processor, resulting in >>improved performance and enhanced throughput. This specially configured version >>can elevate performance on certain applications by as much as 30% to 45% over >>what standard p690 configurations can provide." >> >>"In the standard p690 each POWER4 chip contains two processing cores that share >>an L2 cache. With the p690 HPC option, each chip contains only one processing >>core, making the chip's full I/O and memory bandwidth available to the single >>processor." >> >>It's about $4M, in a 32-way configuration. > >I still wonder though. The PDF you pointed to only talked about SMP >interleaving within the MCM. It gave no indication if inter-MCM memory >interleaving leaving once again the impression of NUMA. Also, if the CHIP is >reduced to one processor core in the HPC configuration, how does that affect the >number of CPUs per MCM and does it necessarily improve NUMA latencies? Maybe it >only improves MCM performance. > >MH In it's 'standard' config, it is a NUMA machine. http://researchweb.watson.ibm.com/journal/rd/461/tendler.pdf Search for 'System Balance'. "The multi-MCM configuration provides a worst-case memory access latency of slightly greater than 10% more than the best-case memory access latency maintaining the flat memory model, simplifying programming." But the HPC option seems to end that latency, with full memory bandwidth over the MCMs & CPUs. But I am still getting clarification on this.
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