Author: Robert Hyatt
Date: 12:26:23 11/17/98
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On November 16, 1998 at 19:45:31, Terry Presgrove wrote: >I just read that AMD's new K-7 chip will support multi-processing >but I'm not sure it will be shared memory? Here is the quote from >AMD's home page. "About the AMD-K7(TM) Processor >The AMD-K7 processor with 3DNow!(TM) technology is a Microsoft® Windows® >compatible, seventh-generation design featuring a deeply pipelined, nine-issue >superscalar microarchitecture optimized for high clock frequency; a superscalar >pipelined floating point unit; 128KB of on-chip level one (L1) cache; a >programmable high-performance backside L2 cache interface; and a 200 MHz Alpha >EV6 compatible system bus interface with support for scalable multiprocessing. >The AMD-K7 processor is slated for introduction in the first half of 1999 and is >planned to operate at clock frequencies greater than 500 MHz." >I guess the key phrase is "scalable multiprocessing" anyone have a clue >as to what this means? I am particularly interested in its impact on chess >programs? Here's the main issue... Intel owns the "IO_APIC" design for handling interrupts at the hardware level. They won't (so far) license it to anyone else. This means that APIC interrupt handling is only going to apply to the Intel processors. OK for step 1. Next, Linux and NT support SMP, but *only* via the APIC interrupt handling approach. Which again means only on Intel processors. So the answer is "yes, the K7 *can* be used in a SMP computer, but no, it won't be usable for a long time, if ever, because no one wants to rewrite the interrupt handlers to use the AMD interrupt controller design." When enough are "out" Linux will likely support it. But don't look for something very quickly... because until there is an operating system to support it, it is going to be hard to get a vendor to design/build SMP motherboards for that processor... and until they do, there won't be any O/S support... and on and on... :)
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