Author: Keith Evans
Date: 12:43:51 02/17/04
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On February 17, 2004 at 14:52:31, Vincent Diepeveen wrote: >On February 17, 2004 at 13:02:01, Keith Evans wrote: > >>many gates Marc Boule's move generator takes in a Virtex, and my own attempt >>wasn't much better. But anyways I have actually implemented a hardware based >>move generator, and ran some perft tests on it, so I do understand Belle style >>move generation and its limitations. However I don't know if Chrilly did a Belle >>style generator or not. I didn't go further with bolting search and eval onto >>the Belle style move generator because I didn't want to have to make a huge $$$ >>investment to get something competitive. > >Chrilly quantified these move generators as complete beginners stuff. Well of course since they published all the details to implement them, then anybody can do so. (You can even download Marc Boule's VHDL code for kicks.) Chrilly did hang out with Ken Thompson for a while to pick his brain. I'll bet that Chrilly's generator is actually simpler than a Belle-style generator - not that this makes it inferior. Or he may just have figured out a better way to exploit the resources in the Virtex parts and it's equally complex. (For example maybe he is using the on-chip "tristate" busses for arbitartion rather than a big tree. Or he doesn't handle promotions? Castling? ...) Since I don't know what he did, then the mystery makes me interested. If I did know, then I would probably be disappointed. Given that he only runs at 30 MHz I can infer something about his longest combinatorial path... (We have a pretty complicated DSP implemented in a Virtex-II and get it to run at 80 MHz without really doing anything special to target an FPGA.) But obviously Chrilly did not figure out some great mystery, otherwise he wouldn't need to throw so much hardware at the problem. With so many powerful CPUs in the mix you could just leave the FPGAs idle and still have a competitive program. -K
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