Author: Gerd Isenberg
Date: 03:15:13 08/07/04
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On August 06, 2004 at 19:27:52, Peter Berger wrote: >Compairing two computers - a PIV 3.2HT and an Athlon 64 3200+, both running >Windows XP and bench commands of chessprograms > >Shredder Classic ran with 64 MB hash > >Crafty is Crafty 19.15SE executable, hash 48M , hashp 12M, (mt=1) > >Athlon 64 3200+ > >Phalanx 493909 12% faster >Shredder Classic 2.11 22.7% faster >Crafty 19.15 1115929 52 12.307692 20% slower > >PIV 3.2GHzHT > >Phalanx 441072 >Shredder Classic 1.72 >Crafty 19.15 1349496 43 14.884 > >Hmm - so what to conclude ? > >Peter So you compare same 32-bit executables on PIV versus AMD64-32bit mode. PIV's hyper threading has only negligible effect for single threaded programs, even if the OS supports it. It would be interesting to compare with some fast Athlon32 as well, to look for some possible AMD64 improvements in 32-bit mode (branch prediction, cache sizes, but still 8-gp-registers). One conclusion is that AMD64-32bit mode is faster with 2.2GHz than PIV with 3.2 MHz - not a big surprise, since instructions per cycle is most often better for AMD. Anyway there are instruction sequences, loops and/or subroutines which perform relative better on PIV, due to it's architecture with the so called code trace cache, branch prediction issues and whatever more. Memory usage and chache sizes are important too. So the second conclusion is that some programs based on their internal structure gain more than others from AMD64, even in 32-bit mode. Of course also a matter of what compiler and optimization settings were used to produce the executables. It is possible to optimize in (relative) favour for PIV with some compilers. All programs would profit even more from 64-bit mode (GCC for linux64 or ms beta OS as well as beta MSC compiler), basically due to more available general purpose registers. Bitboard programs gain a bit more from wider 64-bit registers, since one bitboard covers only 1/16 instead of 2/8 of all available gp-registers (ignoring shadow registers). Specially variable 64-bit shifts gain a lot. OTOH two bitwise 32-bit "none-overflow" instructions (and/or/not/xor) are not so much slower than one appropriate 64-bit instruction, due to possible parallel execution of two independent 32-bit instructions, while one 64-bit instruction is more likely to introcude register stalls with leading/trailing dependent instructions. Gerd
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