Author: Dieter Buerssner
Date: 05:14:16 05/01/05
Go up one level in this thread
On May 01, 2005 at 07:43:35, Gerd Isenberg wrote:
>On May 01, 2005 at 05:15:57, Dieter Buerssner wrote:
>
>>For real 64 bit multiplications/devisions: How is the cycle count for these
^ that typo looks horrible.
>>instructions on AMD64? I would fear, that it needs quite a few more cycles, than
>>32 bit counter parts.
>
>IMUL mreg16 F7h 11-101-xxx VectorPath 4
>IMUL mreg32/64 F7h 11-101-xxx Double 3/ 5
>MUL mreg16 F7h 11-100-xxx VectorPath 4
>MUL mreg32/64 F7h 11-100-xxx Double 3/ 5
>DIV mreg16/32/64 F7h 11-110-xxx VectorPath 23/39/71
>IDIV mreg16/32/64 F7h 11-111-xxx VectorPath 26/42/74
Gerd, thanks for positing the numbers. I am not sure, I understand the table.
F7h is the upcode prefix for 64 bit operations? And each of the mul operations
will produce a 128 bit result (with obvious zero bits starting for a smaller
multiplicand)? If this is correct, what is the cycle count for the "old" MUL
mreg32 that multiplies two 32 bit words?. This would be the real comparision for
my little example. "mul number_of_entries", in the typical 32 bit engine as
32*32->64, in the 64 bit engine 64*64->128.
Just curious about the MUL mreg16 - doesn't it need another upcode prefix (like
many 16 bit operations on x86-32)?
Similar, the DIV above is on 64 bit pair dx:ax and produces 2 64 bit results for
division and modulo just like the normal div for 32-bit?
Cheers,
Dieter
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