Author: Robert Hyatt
Date: 18:42:28 02/07/06
Go up one level in this thread
On February 07, 2006 at 16:28:53, h.g.muller wrote:
>I guess I misread your previous message, I thought you referred to the variable
>latency because of the initial access, but you were talking about the follow
>up... :-(
>
>I think it would be a good idea to align the hash table with cache-line
>boundaries so that this will not occur. In a 64-byte cache lines you could put
>four 16-byte entries, so that a single entrie never straddles a boundary. The
>rehashing scheme coud be designed such that you try all 4 entries in that cache
>line before trying anything else (or accept a failure):
>
>if(TP[hash].lock==key
> TP[hash^=16].lock==key ||
> TP[hash^=32].lock==key ||
> TP[hash^=16].lock==key)
>{/* process hit at TP[hash] */}
>else
>{/* process miss */}
I suspect most of us do this to some extent. For example I have always tried to
force hash table to 64.
But don't forget, line-size on the PIV is not 64. It is 128. So this changes
from generation to generation. (BTW, PIV has different line size for L1 vs L2
as well, which further complicates this...) :)
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